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| document number: mc33810 rev. 6.0, 12/2008 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2006 - 2008. all rights reserved. automotive engine control ic the 33810 is an eight channel output driver ic intended for automotive engine cont rol applications. the ic consists of four integrated low side drivers and four low side gate pre-drivers. the low side drivers are suitable for driving fuel injectors, so lenoids, lamps, and relays. the four gate pre-driver s can function either as ignition igbt gate pre-drivers or as g eneral purpose mosfet gate pre- drivers. when configured as ignition igbt gate pre-drivers, additional features are enabled such as spar k duration, dwell time, and ignition coil current sense. when configured as a general purpose gate pre- driver, the 33810 provides external mosfets with short circuit protection, inductive flyback protection and diagnostics. the device is packaged in a 32 pin (0.65mm pitch) exposed pad soic. features ? designed to operate over the range of 4.5v vpwr 36v ? quad ignition igbt or mosfet gate pre-driver with parallel/spi and/or pwm control ? quad injector driver with parallel/spi control ? interfaces directly to mcu using 3.3v / 5.0v spi protocol ? injector driver current limit - 4.5a max. ? independent fault protection and diagnostics ? vpwr standby current 10 a max. ? pb-free packaging designated by suffix code ek figure 1. mc33810 simplified application diagram engine control 33810 ordering information device temperature range (t a ) package mcz33810ek/r2 -40c to 125c 32 soicw-ep vpwr vdd si sclk cs so din0 din3 gin0 out en spkdur nomi maxi out0 out1 out2 out3 gnd fb0 gd0 fb1 gd1 fb2 gd2 fb3 gd3 rsp rsn mosi sclk miso etpu etpu gpio etpu etpu etpu mcu 33810 v bat v bat v bat v bat v bat v bat v bat v bat cs etpu gin3 etpu v dd vbat ek suffix (pb-free) 98asa10556d 32 pin soicw ep
analog integrated circuit device data 2 freescale semiconductor 33810 internal block diagram internal block diagram figure 2. 33810 simplifi ed internal block diagram gate control current limit temperature limit short/open vpwr, vdd oscillator din0 v2.5 vpwr din1 din2 din3 ~50 a ~50 a ~50 a ~50 a gin0 gin1 gin2 gin3 ~50 a ~50 a ~50 a ~50 a vdd ~5 0a spkdur so v dd si sclk cs ~50 a v dd logic control spi outen + r s llimit voc1 ? outputs 0 to 3 75 a out1 out2 out3 nomi exposed pad vdd ~50 a v dd bandgap maxi + ? spi + ? + ? dac dac + ? v pwr vlvc voc gpgd low v clamp clamp 100 a gate drive control spark duration parallel control pwm controller nomi,maxi dac spark dac under-voltage por, over-voltage v8.0 analog v2.5 logic bias nomi maxi rsp rsn gd1 gd2 gd3 gd0 fb1 fb2 fb3 out0 + ? spi open secondary fb0 gnd interface exposed pad ~15 a ~15 a only gpgd analog integrated circuit device data freescale semiconductor 3 33810 pin connections pin connections figure 3. 33810 pin connections table 1. 33810 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 13 . pin number pin name pin function formal name definition 8 vdd input digital logic supply voltage the vdd input supply voltage determi nes the interface voltage levels between the device and the mcu, and is used to supply power to the serial out buffer (so), spkdur buffer, maxi, nomi, and pull-up current source for the chip select ( cs ). 6 si input serial input data the si input pin is used to receive serial data from the mcu. 5 sclk input serial clock input the sclk input pin is used to clock in and out the serial data on the si and so pins, while being addressed by the cs . 4 cs input chip select the chip select input pin is an active low signal sent by the mcu to indicate that the device is being addr essed. this input requires cmos logic levels and has an internal active pull-up current source. 7 so output serial output data the so output pin is used to transmit serial data from the device to the mcu. 10, 11, 12, 13 din0,din1, din2,din3 input driver input 0, driver input 1, driver input 2, driver input 3 active high input control for injector outputs out0 - 3. the parallel input data is logically or?d with the corresponding spi input data register contents. 24, 23, 22, 21 gin0,gin1, gin2,gin3 input gate driver input 0 gate driver input 1 gate driver input 2 gate driver input 3 these pins are the active high i nput control for igbt/general purpose gate driver outputs 0 - 3. the parallel input data is logically or'd with the corresponding spi input data register contents in general purpose mode only. 20 spkdur output spark duration output this pin is the spark duration output. this open drain output is low while feedback inputs fb0 through fb3 are above the programmed spark detection threshold. 25 vpwr input analog supply voltage vpwr is the main voltage input for al l internal analog bias circuitry. exposed pad (bottom of package) gnd ground ground the exposed pad is the only ground re ference for analog, digital and power ground connections. as such, it must be soldered directly to a low impedance ground plane for both electric al and thermal considerations. for more information about this pac kage, please see application note an2409 on the freescale website, www.freescale.com gnd out0 fb0 gd0 cs sclk si so vdd outen din0 din1 din2 din3 gd1 fb1 out1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 out2 fb2 gd2 maxi nomi rsn rsp vpwr gin0 gin1 gin2 gin3 spkdur gd3 fb3 out3 analog integrated circuit device data 4 freescale semiconductor 33810 pin connections 9 outen input output enable the output enable pin ( outen ) is an active low input. when the outen pin is low, the device outputs are active. the outputs are disabled when outen is high. 29 maxi output maximum ignition coil current this pin is the maximum ignition coil current output flag. this output is asserted when the igbt collector-emitter current exceeds the selected level of the dac. this signal also latches off the gate pre-drive outputs when configured as a general purpose gate pre-driver. the maxi current level is determined by the vo ltage drop across an external sense resistor connected to pins rsp and rsn. 28 nomi output nominal ignition coil current this pin is the nominal ignition coil current output flag. this output is asserted when the igbt collector-emitter current exceeds the level selected by the dac. 2, 15, 31, 18 fb0 - fb3 input feedback voltage sense in igbt ignition gate pre-driver m ode, these feedback inputs monitor the igbt's collector voltage to provide the spark duration timer control signal. 3, 14, 30,19 gd0 -gd3 output gate drive output igbt/general purpose gate pre-dr iver outputs are controlled by gin0 - gin3 . pull-up and pull-down current sources are used to provide a controlled slew rate to an external igbt or mosfet connected as a low side driver. 26 rsp input resistor sense positive this pin is the positive input of a current sense amplifier. 27 rsn input resistor sense negative this pin is the negative input of a current sense amplifier. 1, 16, 32, 17 out0 -out3 output low side injector driver output these pin are the open drain low side injector driver outputs. table 1. 33810 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 13 . pin number pin name pin function formal name definition analog integrated circuit device data freescale semiconductor 5 33810 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. ratings symbol value unit electrical ratings vpwr supply voltage (1) v pwr -1.5 to 45 v dc vdd supply voltage (1) v dd -0.3 to 7.0 v dc spi interface and logic input voltage ( cs , si, so, sclk, outen , din0 - din3, gin0 - gin3, spkdur , nomi, maxi, rsp,rsn) v il v ih -0.3 to vdd v dc igbt/general purpose gate pre-driver drain voltage (v fb0 to v fb3 ) v fb -1.5 to 60 v dc injector output voltage (outx) v outx -1.5 to 60 v dc general purpose gate pre-driver output voltage (gdx) v gdx -0.3 to 10 v dc output clamp energy (out0 to out3)(single pulse) t junction = 150c, i out = 1.5 a e clamp 100 mj output clamp energy (out0 to out3)(continuous pulse) t junction = 125c, i out = 1.0 a (max injector frequency is 70 hz) e clamp 100 mj output continuous current (out0 to out3) t junction = 150c i ossss 2.0 a maximum voltage for rsn and rsp inputs v rsx -0.3 - vdd v dc frequency of spi operation (vdd = 5.0 v) ? 6.0 mhz esd voltage (2), (3) human body model (hbm) machine model (mm) charge device model (cdm) v esd1 v esd2 v esd3 2000 200 750 v thermal ratings operating temperature ambient junction2 case t a t j t c -40 to 125 -40 to 150 -40 to 125 c storage temperature t stg -55 to 150 c power dissipation (t a = 25 c) p d 1.7 w peak package flow temperature during solder mounting dwb suffix ew suffix t solder 240 245 c thermal resistance junction-to-ambient junction- to-lead junction-to-flag r ja r jl r jc 75 8.0 1.2 c/w notes 1. exceeding these limits may cause malf unction or permanent damage to the device. 2. esd data available upon request. 3. esd testing is performed in accordance with the human body model (hbm) (aec-q100-002), the machine model (mm) (aec-q100- 003), and the charge device model (cdm), robotic (aec-q100-011). analog integrated circuit device data 6 freescale semiconductor 33810 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted u nder conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where typical values refl ect the parameter?s approx. average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit power input (vdd, vpwr) supply voltage (4) fully operational full parameter specification v pwr ( fo ) 4.5 9.0 ? 36 18 v supply current all outputs disabled (normal mode) i vpwr ( on ) ? 10.0 14.0 ma sleep state supply current (must have v dd 0.8 v for sleep state), v pwr = 18 v i vpwr (ss) ? 15 30 a v pwr over-voltage shutdown threshold voltage (5) v pwr( ov) 36.5 39 42 v v pwr over-voltage shutdown hysteresis voltage v pwr(ov-hys) 0.5 1.5 3.0 v v pwr under-voltage shutdown threshold voltage (6) v pwr( uv) 3.0 4.0 4.4 v v pwr under-voltage shutdown hysteresis voltage v pwr( uv-hys) 100 200 300 mv v pwr low operating voltage (low-voltage reported via the spi) (7) v pwr( lov) 5.3 ? 8.99 v vdd supply voltage v dd 3.0 ? 5.5 v vdd supply current static condition and does not include vdd current out of device i vdd ? ? 1.0 ma vdd supply under-voltage (sleep state) threshold voltage (8) v dd(uv) 0.8 2.5 2.8 v injector driver outputs (out 0:3) drain-to-source on resistance i out = 1.0 a, t j = 125 c, vpwr = 13 v i out = 1.0 a, t j = 25 c, vpwr = 13 v i out = 1.0 a, t j = -40 c, vpwr = 13 v r ds (on) ? ? ? ? 0.2 ? 0.3 ? ? output self limiting current i out (lim) 3.0 ? 6.0 a output fault detection voltage threshold (9) outputs programmed off (open load) outputs programmed on (short to battery) v out(flt-th) 2.0 2.5 3.0 v output off open load detection current v drain = 18 v, outputs programmed off i (off)oco 40 75 100 a output on open load detection current current less then specification value considered open i (on)oco 20 100 200 ma notes 4. these parameters are guaranteed by design, but not production te sted. fully operational means driver outputs will toggle as e xpected with input toggling. spi is guarant eed to be operational when vpwr > 4.5 v. spi may not report correctly when vpwr < 4.5 v. 5. over-voltage thresholds minimu m and maximum include hysteresis. 6. under-voltage thresholds minimu m and maximum include hysteresis. 7. device is functional provided t j is less than 150c. some table parameters may be out of specification. 8. device in sleep state, returns from sleep state with power on reset. 9. output fault detection thresholds with outputs programmed off. output fault detect thresholds are the same for output open an d shorts. analog integrated circuit device data freescale semiconductor 7 33810 electrical characteristics static electrical characteristics injector driver outputs (out 0:3) (continued) output clamp voltage 1 i d = 20 ma v oc1 48 53 58 v output leakage current vdd = 5.0 v, v drain = 24 v, open load detection current disabled vdd = 5.0 v, v drain = v oc - 1.0 v, open load detection current disabled vdd = 0 v, v drain = 24 v, sleep state i out (lkg) ? ? ? ? ? ? 20 3000 10 a over-temperature shutdown (10) t lim 155 ? 185 c over-temperature shutdown hysteresis (10) t lim (hys) 5.0 10 15 c ignition (igbt) gate driver parameters (gd 0:3 fb0:3) gate drive output voltage i gd = 500 a i gd = -500 a v gs (on) v gs (off) 5 0 7.0 0.375 9.0 0.5 v sleep mode gate to source resistor r gs (pulldow n) 100 200 300 k sleep mode fbx pin leakage current vdd = 0 v, v fbx = 24 v, i fbx (lkg) ? ? 1.0 a feedback sense current (fbx input current) fbx = 18 v, outputs programmed off i fbx(flt-sns) 1.0 a gate drive source current (1 v gd 3) i gatedrive 650 780 950 a gate drive turn off resistance r ds(on) 500 ? 1000 soft shutdown function (voltag es referenced to igbt collector) low voltage flyback clamp driver command off, soft shutdown enabled, gdx = 2.0 v v lvc vpwr +9.0 vpwr +11 vpwr + 13 v spark duration comparator threshold (referenced to ic ground tab) rising edge relative to vpwr v th-rise 18 21 24 v spark duration comparator threshold (referenced to ic ground tab) (11) falling edge relative to vpwr, default = 5.5 v assuming ideal external 10:1 voltage divider. voltage measured at high end of divider, not at pin. tolerance of divider not included v th-fall 1.2 4.9 7.4 9.9 2.75 5.5 8.2 11.00 3.6 6.1 9.1 12.1 v open secondary comparator threshold (referenced from primary to rising edge relative to gnd. no hy steresis with 10:1 voltage divider. v th-rise 11.5 ? 15.5 v current sense comparator (rsp, rsn) nomi trip threshold accuracy - steady state condition 3.0 a across 0.02 (rsp - rsn = 60 mv) 10.75 a across 0.04 (rsp - rsn = 430 mv) nomi tripta -10 ? 10 % notes 10. this parameter is guaranteed by design, however is not production tested. 11. assuming ideal external 10:1 voltage di vider. tolerance of 10:1 voltage divider is not included. voltage is measured on the high end of divider - not at the pin. 10:1 n.3.a 10:1 voltage divider is produced using two resistors with a 9:1 resistance ratio by the ba sic formula: table 3. static elec trical characteristics characteristics noted under conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where typical values reflect t he parameter?s approx. average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit where r2 = 9xr1 vout vin ----------------- - r1 r1 r2 + ---------------------- = analog integrated circuit device data 8 freescale semiconductor 33810 electrical characteristics static electrical characteristics current sense comparator (rsp, rsn) (continued) maxi trip threshold accuracy steady state condition 6.0 a across 0.02 (rsp - rsn = 120 mv) 21 a across 0.04 (rsp - rsn = 840 mv) maxi tripta -7.5 ? 7.5 % maxi trip point during overlapping dwell maxi tripod -35 ? +35 % input bias current rsp and rsn i biasrsx -50 ? 50 a comparator hysteresis voltage nomi maxi nomi hys maxii hys 40 40 ? ? 70 70 % of vt input voltage range (maximum voltage between rsn and rsp) (12) vcmvr cmvr 0.0 ? 2.0 v ground offset voltage range (12) maximum offset between rsn pi n and ic ground (exposed pad) vgnd ovr -0.3 ? 0.3 v general purpose gate driver parameters (gd 0:3) gate drive sink and source current i gd 1.0 2.0 5 ma gate drive output voltage i gd = 1.0 ma i gd = -1.0 ma v gs (on) v gs (off) 5.0 0.0 7.0 0.2 9.0 0.5 v v short to battery fault detection voltage threshold v dd = 5.0 v, outputs programmed on programmable from 0.5 to 3.0 v in 0.5 v increments. ( table 14 ) v ds(flt-th) -35% +35% v open fault detection voltage threshold (referenced to ic ground tab) v dd = 5.0 v, outputs programmed off v ds(flt-th) 2.0 2.5 3.0 v output off open load detection current fbx = 18 v, outputs programmed off i fbx(flt-sns) 50 75 120 a output clamp voltage driver command off, clamp enabled, v gate = 2.0 v v oc 48 53 58 v digital interface input logic high-voltage thresholds v ih 0.7 x v dd ? v dd + 0.3 v input logic low-voltage thresholds v il gnd - 0.3 ? 0.2 x v dd v input logic-voltage hysteresis v hys 100 ? 400 mv input logic capacitance c in ? ? 20 pf sleep mode input logic current v dd = 0 v i logic_ss -10 ? 10 a input logic pull-down current 0.8 to 5.0 v (din x and gin x ) i logic_pd 30 50 100 a notes 12. this parameter is guaranteed by desi gn, however it is not production tested. table 3. static elec trical characteristics characteristics noted under conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where typical values reflect t he parameter?s approx. average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit analog integrated circuit device data freescale semiconductor 9 33810 electrical characteristics static electrical characteristics digital interface (continued) input logic pull-down current 0.8 to 5.0 v (si) i si_pd 5.0 15 25 a input logic pull-up current on out_en out_en = 0.0 v, v dd = 5.0 v i out_en _pu -30 -50 -100 a out_en leakage current to v dd out_en = 5.0 v, v dd = 0 v i out_en (lkg) ? ? 50 a sclk pull-down current v sclk = v dd i sclk 5 15 25 a tri-state so output 0 to 5.0 v i triso -10 ? 10 a cs input current cs = v dd i cs -50 ? 50 a cs pull-up current cs = 0 v i cs _pu -30 -50 -100 a cs leakage current to v dd cs = 5.0 v, v dd = 0 v i cs (lkg) ? ? 50 a so input capacitance in tri-state mode c so ? 20 ? pf so high state output voltage i so-high = -1.0 ma v so_high v dd - 0.4 ? ? v so low state output voltage i so-low = 1.0 ma v so_low ? ? 0.4 v nomi, maxi in v10 mode pull-down current nomi, maxi = 0.8 v , v dd = 5.0 v i pd 30 70 100 a spkdur output voltage i spkdur = 1.0 ma v spkdur _lo ? ? 0.4 v output pull-up current for spkdur i spkdur _pv 30 50 100 a nomi, maxi high state output voltage i nomi-high = -1.0 ma i maxi-high = -1.0 ma v i_high v dd - 0.4 ? ? v nomi, maxi low state output voltage i nomi-low = 250 a i maxi-low = 250 a v i_low ? ? 0.4 v table 3. static elec trical characteristics characteristics noted under conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where typical values reflect t he parameter?s approx. average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit analog integrated circuit device data 10 freescale semiconductor 33810 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit power input required low state duration on vpwr for under-voltage detect v pwr 0.2 v t uv 1.0 ? ? s required low state duration on vdd for power on reset v dd 0.2 v t reset 1.0 ? ? s injector drivers output on current limit fault filt er timer (short to battery fault) t sc 30 60 90 s output on open circuit fault filter timer t (on)oc 3.0 7.5 12 ms output retry timer t ref ? 10 15 ms output off open circuit fault filter timer t (off)oc 100 400 s output slew rate (no faster than 1.5 s from off to on and on to off) r load = 14 , v load = 14 v t sr(rise) 1.0 5.0 10 v/ s output slew rate r load = 14 , v load = 14 v t sr(fall) 1.0 5.0 10 v/ s propagation delay (input rising edge or cs to output falling edge) input @ 50%v dd to output voltage 90% of v load t phl 1.0 5.0 s propagation delay (input falling edge or cs to output rising edge) input @ 50%v dd to output voltage 10% of v load t plh 1.0 5.0 s ignition & general purpose gate driver parameters propagation delay (ginx input rising edge or cs to output rising edge) input @ 50%v dd to output voltage 10% of v gs (on) t plh 0.2 1.0 s propagation delay (input falling edge or cs to output falling edge) input @ 50%v dd to output voltage 90% of v gs (on) t phl 0.2 1.0 s ignition parameters open secondary fault timer accuracy (uncalibrated) -35 ? 35 % maximum dwell timer accuracy (uncalibrated) -35 ? 35 % end of spark filter accuracy (uncalibrated) (13) -35 ? 35 % notes 13. this parameter is guaranteed by desi gn, however it is not production tested. analog integrated circuit device data freescale semiconductor 11 33810 electrical characteristics dynamic electrical characteristics general purpose gate driver parameters short to battery fault detection filter timer accuracy vdd = high, outputs programmed on programmable from 30 s to 960 s in replicating increments tolerance of timer after using calibration command tolerance of timer before using calibration command v ds(flt-th) -10 -35 +10 +35 % output off open circuit fault filter timer vdd = 5.0 v, outputs off tolerance of timer before using calibration command t (off)oc 100 400 s pwm frequency 10 hz to 1.28 khz tolerance after using calibration command pwm frequency 10 hz to 1.28 khz tolerance before using calibration command pwm freq pwm freq -10% -35% 10% 35% gate driver short fault duty cycle gd shrt_dc 1.0 3.0 % spi digital interface timing (14) falling edge of cs to rising edge of sclk required setup time t lead 100 ? ? ns falling edge of sclk to rising edge of cs required setup time t lag 50 ? ? ns si to rising edge of sclk required setup time t si (su) 16 ? ? ns rising edge of sclk to si required hold time t si (hold) 20 ? ? ns si, cs , sclk signal rise time (15) t r (si) ? 5.0 ? ns si, cs , sclk signal fall time (16) t f (si) ? 5.0 ? ns time from falling edge of cs low-impedance (17) t so (en) ? ? 55 ns time from rising edge off cs to so high-impedance (18) t so (dis) ? ? 55 ns time from falling edge of sclk to so data valid (19) t valid ? 25 55 ns sequential transfer rate time required between data transfers t str 1.0 ? ? s digital interface calibrated timer accuracy t timer ? ? 10 % un-calibrated timer accuracy t timer ? ? 35 % notes 14. these parameters are guaranteed by design. production test equipment uses 1.0 mhz, 5.0 v spi interface. 15. this parameter is guaranteed by desi gn, however it is not production tested. 16. rise and fall time of incoming si, cs and sclk signals suggested for desi gn consideration to prevent t he occurrence of double pulsing. 17. time required for valid output status data to be available on so pin. 18. time required for output states data to be terminated at so pin. 19. time required to obtain valid data out from so following the fall of sclk with 200 pf load. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions of 3.0 v vdd 5.5 v, 9.0 v vpwr 18 v, -40 c tc 125 c, and calibrated timers, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with vpwr = 13 v, ta = 25 c. characteristic symbol min typ max unit analog integrated circuit device data 12 freescale semiconductor 33810 electrical characteristics timing diagrams timing diagrams t so(en) cs sclk si so msb out lsb out msb in 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd t valid t so(dis) 0.7 v dd 0.2 v dd t lead 0.2 v dd t lag t si(su) t si(hold) analog integrated circuit device data freescale semiconductor 13 33810 functional description functional pin description functional description functional pin description analog supply voltage (vpwr) the vpwr pin is the battery input to the 33810 ic. the vpwr pin requires external reverse battery and transient protection. all ic analog current and internal logic current is provided from the vpwr pin. with vdd applied to the ic, the application of vpwr will perform a por. digital logic supply voltage (vdd) the vdd input pin is used to determine communication logic levels between the microprocessor and the 33810 ic. current from vdd is used to dr ive so output and the pull-up current for cs . v dd must be applied for normal mode operation. removing v dd from the ic will place the device in sleep mode. with vpwr applied to the ic, the application of v dd will perform a por. ground (gnd) the bottom pad or flag provides the only ground connection for the ic. the vpwr and vdd supplies are both referenced to the gnd pad. the gnd pad is used for both de-coupling the power supplies as well as power ground for the output drivers. although the silicon die is epoxy attached to the top side of the pad, the pad must be grounded for proper electrical operation. serial clock input (sclk) the system clock (sclk) pi n clocks the internal shift register of the 33810. the si data is latched into the input shift register on the rising edge of sclk signal. the so pin shifts status bits out on the falling edge of sclk. the so data is available for the mcu to read on the rising edge of sclk. with cs in a logic high state, signals on the sclk and si pins will be ignored and the so pin is tri-state chip select ( cs ) the system mcu selects the 33810 to receive communication using the chip select ( cs ) pin. with the cs in a logic low state, command words may be sent to the 33810 via the serial input (si) pin, and status information is received by the mcu via the serial output (so) pin. the falling edge of cs enables the so output and transfers status information into the so buffer. rising edge of the cs initiates the following operation: disables the so driver (high-impedance) activates the received command word, allowing the 33810 to activate/deactiv ate output drivers. to avoid any spurious data, it is essential that the high-to- low and low-to-high transitions of the cs signal occur only when sclk is in a logic low state. internal to the 33810 device is an active pull-up to vdd on cs . serial input data (si) the si pin is used for serial instruction data input. si information is latched into the input register on the rising edge of sclk. a logic high state present on si will program a one in the command word on the rising edge of the cs signal. to program a complete word, 16 bits of information or multiples of 8 there of must be entered into the device. serial output data (so) the so pin is the output from the shift register. the so pin remains tri-stated until the cs pin transitions to a logic low state. all normal operating drivers are reported as zero , all faulted drivers are reported as one . the negative transition of cs enables the so driver. the si / so shifting of the data follows a first-in-first-out protocol, with both input and ou tput words transferring the most significant bit (msb) first. output enable ( outen ) the outen pin is an active low input. when the outen pin is low, all the device outp uts are active. the outputs are all disabled when outen pin is high. spi and parallel communications are still active in either state of outen . feedback voltage sensor (fb0-fb3) the fbx pin has multiple functions for control and diagnostics of the external mosfet/igbt ignition gate driver. in ignition (igbt) gate driv er mode, the feedback inputs monitor the igbt's collector voltage to provide the spark duration timer control signal. the spark duration timer monitors this input to determine if the secondary clamp function should be activated. in secondary clamp mode, the igbt's collector voltage is internally clamped to v pwr +11v. in the general purpose gate driver mode, this input monitors the drain of an external mosfet to provide short- circuit and open circuit detection by monitoring the mosfet's drain to source voltage. the filter timer and threshold voltage are easily programmed through spi (see tables 18 and 19 for spi messages). in general purpose gate driver mode the fbx pin also provides a drain to gate clamp fo r fast turn off of inductive loads and external mosfet protection. gate driver output (gd0-gd3) the gd x pins are the gate drive outputs for an external mosfet or igbt. internal to th e device is a gate to source resistor designed to hold the ex ternal device in the off state while the device is in the por or sleep state. analog integrated circuit device data 14 freescale semiconductor 33810 functional description functional pin description low side injector driver output (out0 - out3) out0 - out3 are the open drain low side (injector) driver outputs. the drain voltage is actively clamped during turn off of inductive loads. these outputs can be connected in parallel for higher current loads provided the turn off energy rating is not exceeded. resistor sense positive (rsp) resistor sense positive - posi tive input of a current sense amplifier. the ignition coil current is monitored by sensing the voltage across an external resistor connected between rsp and rsn. the output of the curr ent sense amplifier feeds the inputs of the nomi and maxi comparators. note: rsn and rsp must be grounded in v10 mode. resistor sense negative (rsn) resistor sense negative - negative input of a current sense amplifier. the ignition coil current is monitored by sensing the voltage across an exte rnal resistor connected to rsp and rsn. the output of the current sense amplifier feeds the inputs of the no mi and maxi comparators. note: rsn and rsp must be grounded in v10 mode. nominal ignition co il current (nomi) nominal ignition coil current output flag. this output is asserted when the output current exceeds the level selected by the dac. nomi can be configured as an input pin for v10 mode applications where the gate drive needs to be latched off by another device?s maxi current sense amplifier output. the nomi input will latch off gate dr ivers 5 and 6 when configured as a v10 mode ignition gate driver see figure 10. spark duration output (spkdur) spkdur is the spark duration output. this open drain output is low while feedback inputs fb0 through fb3 are above the programmed spark detection threshold. this output indicates an ignition flyback event. each feedback input (fb0 - fb3) is logically or'd to drive the spkdur output. there is a 50 a pull up current source connected internally to the spkdur pin. maximum ignition coil current (maxi) maximum ignition coil current output flag. this output is asserted when the output ignition coil current exceeds the selected level of the dac. this signal also latches off the gate drive outputs when configured as an ignition gate driver. the maxi current level is determine d by the voltage drop across an external sense resistor connected to pins rsp and rsn. maxi can be configured as an input pin for v10 applications where the gate drive needs to be latched off by another devices maxi current sense amplifier output. the maxi input will latch off gate drivers 7 and 8 when configured as ignition gate drive outputs see figure 10. driver input (din0-din3), gate driver input (gin0-gin3) parallel input pins for out0-out3 low side drivers and gd0-gd3 gate drivers. each parallel input control pin is active high and has an internal pull-down current sink. the parallel input data is logically or?d with the corresponding spi input data register contents, except for the ignition mode igbt drivers. they are only controlled by the parallel inputs gin0-gin3. in gpgd mode, gi n0-gin3 are logically or?d with spi input data. all outputs are disabled when the outen pin is high, regardless of the state of the command inputs. analog integrated circuit device data freescale semiconductor 15 33810 functional description functional internal block description functional internal block description figure 4. functional internal block diagram power supply/por the 33810 is designed to operate from 4.5 to 36 v on the vpwr pin. the vpwr pin supplies power to all internal regulators, analog, and logic circuit blocks. the vdd supply is used for setting communication threshold levels and supplying power to the so driver. this ic architecture provides a low quiescent current sleep mode. applying vpwr and vdd to the device will generate a power on reset (por) and place the device in the normal state. the power on reset circuit incorporates a timer to prevent high frequency transients from causing a por. mcu interface and output control this component provides parallel input pins for out0- out3 low side drivers and gd0-gd3 gate drivers. each parallel input control pin is active high and has an internal pulldown current sink. the parallel input data is logically or?d with the corresponding spi input data register contents. all outputs are disabled when the outen pin is high, regardless of the state of the command inputs. injector drivers: out0 ? out3 these pins are the open drain low side (injector) driver outputs. the drain voltage is actively clamped during turn off of inductive loads. these outputs can be connected in parallel for higher current loads, provided the turn off energy rating is not exceeded. ignition gate pre- drivers: gd0 ? gd3 these pins are the gate drive outputs for an external mosfet or igbt. internal to th e device is a gate to source resistor designed to hold the ex ternal device in the off state while the device is in the por or sleep state. analog integrated circuit device data 16 freescale semiconductor 33810 functional device operation operational modes functional device operation operational modes power supply the 33810 is designed to operate from 4.5 to 36 v on the vpwr pin. the vpwr pin supplies power to all internal regulators, analog and logic circuit blocks. the vdd supply is used for setting communication threshold levels and supplying power to the so driver. this ic architecture provides flexible microprocessor interfacing and low quiescent current sleep mode. power-on reset (por) applying v pwr and v dd to the device will generate a power on reset (por) and place the device in the normal state. the power on reset circuit incorporates a filter to prevent high frequency transie nts from causing a por. all outputs are disabled when the outen input pin is high regardless of the spi contro l registers or the logic level on the parallel input pins. with the outen pin high, spi messages may be sent and received by the device. upon enabling the device ( outen low), outputs will be activated based on the state of the comm and register or parallel input. sleep state sleep state is entered when the v dd supply voltage is removed from the vdd pin. in sleep state all outputs are off. applying v dd will force the device to exit the sleep state and generates a por. normal state the default normal state is entered when power is applied to the vpwr and vdd pins. control register settings from a power-on reset (por) are as follows: ? all outputs off ? ignition gate driver mode enabled (igbt ignition mode). ? pwm frequency and duty cycle control disabled. ? off state open load detection enabled (lsd) ? maxi dac set to 14 a, nomi dac set to 5.5a ? spark detect level vil dac set to v pwr +5.5v ? open secondary timer set to 100 s ? dwell timer set 32ms ? soft shutdown disabled ? low-voltage flyback clamp disabled ? dwell overlap maxi offset disabled modes of operation in normal state, the 33810 gate driver has three modes of operation, ignition mode, gpgd (general purpose gate driver) mode and v10 mode.the operating mode of each gate driver may be set individually and is programmed using the mode select command. mode select command the mode select command is used to set the operating mode for the gdx gate driver outputs, over/ under-voltage operation and to enable v10 mode and the pwm generators. the mode select command programmable features are listed below. ? ignition/gpgd mode select (gate drivers) ? v10 mode enable ? over/under-voltage operation for all drivers ? gpgd pwm controller enable ignition/gpgd mode select the ignition/general purpose ga te driver mode select bits determine independently, the oper ating mode of each of the gdx gate driver outputs. bits 8,9,10,11 correspond to gd0, gd1, gd2, gd3 respectively. setting the bit to a logic 0 sets the gdx driver to the ignition mo de. setting the bit to a logic 1 commands the gdx driver to the general purpose mode and disables the ignition features for that particular gate driver (except the maxi curr ent shutdown feature). further information on gdx gate driver in ignition mode and general purpose mode is provided later in this section of the data sheet. v10 mode enable bit the v10 enable bit allows the user to configure the device for 10 cylinder applications. when the v10 mode is enabled, the device configures the nomi pin and maxi pin as digital inputs rather than outputs. the new maxi input pin receives table 5. operational states vpwr vdd outen outputs state l l x off power off l h x off por h l x off sleep h x off por h x off por l x off sleep h h l active normal h h h off normal analog integrated circuit device data freescale semiconductor 17 33810 functional device operation operational modes the maxi shutdown signal for gd0 and gd2 and the new nomi input pin receives the maxi shutdown signal for gd1 and gd3. further information on v10 mode is provided in the v10 application section. note: rsn and rsp must be grounded in v10 mode. over/under-voltage shutdown/retry bit the over/under-voltage shutdown/retry bit allows the user to select the global over and under-voltage fault strategy for all the outputs. in an over-voltage or under-voltage condition on the vpwr pin, all outputs are commanded off. the over/under-voltage control bit sets the operation of the outputs when returning from ov er/under- voltage. setting the over/under-voltage bit to logic [1] will force all outputs to remain off when v pwr returns to normal le vel. to turn the output on again, the corresponding input pin or spi bit must be reactivated. setting the over/under-voltage bit to logic [0] will command all outputs to resume their previous state when vpwr returns to normal level. table 6 below provides the output state when returning from over or under-voltage. table 6. over-voltage/under-voltage truth table note: the spi bit does not control the gate driver outputs in the ignition mode, only in the gpgd mode. an under-voltage condition on vdd results in the global shutdown of all outputs and rese t of all internal control registers. the v dd under-voltage threshold is between 0.8v and 2.8v pwm x enable bit gate driver outputs prog rammed as general purpose gate drivers may be used as low frequency pwm outputs. the pwm generators are enabled via bits 0 through 3 in the mode select command. bits 0 through 3 correspond to outputs gd0 through gd3 respectively. once the frequency and duty cycle are programmed through the pwm frequency & dc command, the pwm output may be turned on and off through the pwm enable bit. further information on pwm control is provided in th e general purpose gate driver mode section of this data sheet. ignition (igbt) gate driver mode the mc33810 contains dedicated circuitry necessary for automotive igniti on control systems. each gate driver may be individually configured as an ignition gate driver with the following features: ? spark duration signal ? open secondary timer ? soft shutdown control ? low-voltage flyback clamp ? ignition ignition coil current measurement ? maxi output and control ? nomi output ? maximum dwell timer in the ignition mode, several c ontrol strategies are in place to control the igbt for enhanced system performance. information acquired from the fbx pin allows the device to produce a spark duration signal output ( spkdur ) and detect open secondary ignition coils. based on the fbx signal and spark command register settin gs, the device performs the appropriate gate control (low-v oltage flyback clamp, soft shutdown) and produces the spkdur output. the fbx pin is connected to the collector of the igbt through an external 9:1 resistor divider network. the recommended values for the resistor divider network is 36k and 4.02k, with the 36k resist or connected from the igbt collector to the fbx pin and the 4.02k resistor connected from the fbx pin to ground. additional controls to the gate driver are achieved by sensing the current through the external igbt. the resistor sense positive (rsp) and resistor sense negative (rsn) inputs are use to measure the voltage across an external 20 m or 40 m current sense resistor. a gain select bit in the spark command spi command messages should be set to 1 (gain of 2) when using a 20 m current sense resistor. when using a 40 m current sense resist or, the gain select bit should be set to 0 (gain of 1 is the default value). the ignition coil current is com pared with the output of the dacs which have been programmed via the spi commands. the comparison generates the nominal current signal (nomi) and the maximum current signal (maxi). both signals have a low output when the ignition coil current is below the programmed dac value and a high output when the current is above t he programmed dac value. when the gdx output is shutdo wn because of the control strategy, the output may be ac tivated again by toggling the input control. spark command the spark command is an ignition mode command used to program the parameters for the ignition mode features listed below: ? end spark threshold (endsparkth bits) ? open secondary fault timer (osflt bits) ginx dinx input pin spi bit over/ under- voltage control bit outen input pin state when returning from over/under-voltage x x x 1 off x x 1 0 off 0 0 0* 0 off x 1 0* 0 on 1 x 0* 0 on * default setting analog integrated circuit device data 18 freescale semiconductor 33810 functional device operation operational modes ? secondary clamp (secondary clamp bit) ? soft shutdown enable (softshutdn bit) ? ignition ignition coil current amplifier gain (gain sel bit) ? overlapping dwell disable (overlap dwell disable bit) ? maximum dwell enable (maxdwellen bit) ? maximum dwell timer (maxdwelltimer bits) ? end of spark filter timer value spark command address and data bits are listed in table 20 note: gate driver outputs programmed to be general purpose gate drivers are not affected by the spark commands. spark duration signal the spark duration is defined as the beginning of current flow to the end of current flow across the spark plug gap. because the extremely high-voltage ignition coil secondary output is difficult to monitor, corresponding lower voltage signals generated on the ignition coil primary are often used. the fbx pins monitor the ignition coil primary voltage (igbt collector) through a 10 to 1 voltage divider. when the igbt is disabled, the rise in the fbx signal indicates a sparkout condition is occurring at the spark plug gap. the device considers the initial thresholds for spark duration to be v ih = v pwr + 21 v for rising edge as measured on the collector of the igbt. the spark duration falling edge reference is programmable via spi through the end spark threshold bits 0 and 1 (see table 7 ). figure 5 illustrates a typical ignition event with dwell time and spark duration indicated. figure 5. ignition coil charge and spark event v pwr = 16.0v default settings begin spark threshold v ih = v pwr + 21v end spark threshold v il = v pwr +5.5v the pulse width of the spkdur signal is measured by the mcu timer/input capture port to determine the actual spark duration. spark duration informati on is then used by the mcu spark control algorithm to optimize the dwell time. open secondary timer a fault due to open in the ignition coil secondary circuit can be determined by waveforms established on the ignition coil primary during a spark event. the spark event is initiated by the turn off of the igbt. the vo ltage on the collector of the igbt rises up to the igbt?s internal collector to gate clamp voltage (typically 400 volts). collector to gate clamp events normally last 5.0 to 50 s. in an open ignition coil secondary fault condition, the collector to gate clamp event lasts much longer. the oscilloscope waveform in figure 6 and figure 7 compare a normal spark signature with that of an open secondary fault condition signature. figure 6. normal spark event spkdur ~3.0ms dwell time ignition coil current, channel 1: ginx igbt gate drive channel 2: igbt collector voltage channel 3: igbt current @ 5.0a/div 5.0a/div table 7. end spark threshold spark command bit analog integrated circuit device data freescale semiconductor 19 33810 functional device operation operational modes figure 7. open secondary spark event the open secondary timer is initiated on the rising edge of the ignition coil primary spark signal and terminated on the falling edge. the rising edge open secondary threshold is v ih = 135 v at primary, no hysteresis. the falling edge open secondary threshold is v il = 135v. collector to gate clamp durations that last longer than the selected open secondary fault time interval ( table 8 ) indicates a failed spark event. when the open secondary fault time is exceeded and the low-voltage clamp is enabled, the gdx output will activate the low-voltage clamp shown in figure 16. the logic for this low-voltage clamp is defined in figure 9 low-voltage clamp the low-voltage clamp is an internal clamp circuit which biases the igbt's gate voltage in order to control the collector to emitter voltage to vpwr+11v. this technique is used to dissipate the energy stored in the ignition coil over a longer period of time than if the internal igbt clamp were used. in the open secondary fault condition, all of the stored energy in the ignition coil is dissipated by the igbt. this fault condition requires the use of a higher energy rated igbt than would otherwise be needed. the low-voltage clamp spreads out the energy dissipation over a longer period of time, thus allowing the use of a lower energy rated igbt s. the internal low-voltage clamp is connected between the igbt's collector (through an external resistor) and the igbt's gate. the energy stored in the ignition coil is dissipated by the igbt, not the internal clamp. the internal clamp only provides the bias to the igbt. several logical signals are required as inputs to activate the gdx low-voltage clamp fe ature. the gdx low-voltage clamp feature may be disabled through bit 4 of the spark command message. figure 8. low-voltage clamp figure 9. low-voltage clamp logic soft shutdown enable the soft shutdown feature is enabled via the spi by asserting control bit 5 in the spark command message. when enabled, the following events initiate a soft shutdown control of the gate driver. ? outen = high (outputs disabled) ? over-voltage on vpwr pin table 8. open secondary timer spark command bits analog integrated circuit device data 20 freescale semiconductor 33810 functional device operation operational modes ? max dwell time soft shutdown is designed to prevent an ignition spark while turning off the external igbt. the low-voltage clamp is activated to provide the mechanism for a soft shutdown. gain select bit the ignition coil current com parators are used to compare the programmed nomi and m axi dac value with voltage across the external current sens e resistor. when selecting a gain of two, the ignition coil current sense resistor must be reduced from 40m to 20m . overlapping dwell enable bit overlapping dwell occurs when two or more ignition mode drivers are commanded on at the same time. in this condition, with the overlapping dwell bit enabled the maxi dac threshold value is increa sed as a percentage of the nominal programmed value. the percent increase is determined by bit 5 through bit 7 of the dac command. maximum dwell enable bit bit 8, the maximum dwell enable bit allows the user to enable the maximum dwell gate turnoff feature. when the max dwell bit is programmed as logic 0 (disabled) the device will not perform a low-voltage clamp due to max dwell (see figure 9 ). maximum dwell gate turn off feature in automotive igniti on systems, dwell time is defined as the duration of time that an ignition coil is allowed to charge. the mc33810 starts the measure of ti me from the gate drive on command. if the dwell time is greater than the max dwell timer setting ( table 10 ), the offending igni tion gate driver is commanded off. the max dwell gate turn off feature may be disabled via bit 8 of the spark command. when the feature is disabled, the max dwell fault bits are always logic 0. the max dwell timer feature pertains to ignition mode only and does not affect gate dr ivers configured as general purpose gate drivers. the max dwell gate turn off signal is a logically anded with the soft shutdown bit to activate a low-voltage active clamp (see figure 9 ). dac command (digital to analog conversion command) the dac command is an ignition mode command that sets the nominal ignition coil current (nomi) and maximum ignition coil current (maxi) dac values. bits 0 through 4 set the nomi threshold value and, bi ts 8 through 11 set the maxi threshold values. the dac command and default values are listed in the spi command summary table 20 . the nomi output is used by the mcu as a variable in dwell and spark control algorithms. nomi dac bits the nomi output signal is generated by comparing the external current sense resistor differential voltage (resistor sense positive, resistor s ense negative) with the spi programmed nomi dac value. when the nomi event occurs, the nomi output pin is asserted (high). the nomi output is only a flag to the mcu and it?s output does not affect the gate driver. when using a 20 m resistor as the current sense resistor, the gain select of the differential amplifier connected to rsp and rsn, should be set to a gain of 2, via the spi command message spark command (command 0100, hex 4), control bit 6 =1. when using a 40m resistor as the curre nt sense resistor, the gain select of the differential amplifier connected to rsp and rsn, should be set to a gain of 1, via the spi command message spark command (command 0100, hex 4), control bit 6 =0. this is also the default value. the nomi output provides a means to alert the mcu when the ignition coil primary current equals the value programmed into the nomi dac. in v10 mode, the nomi pin is reconfigured as a maxi input pin from a third mc33810 device in the system. in this mode a nomi input has effectively the same control as an internal maxi signal. further information is provided in the v10 mode application sect ion of this data sheet. table 9. overlapping dwell compensation dac command bits analog integrated circuit device data freescale semiconductor 21 33810 functional device operation operational modes maxi dac bits the maxi control block provides a means to shut off all the ignition coil drivers if the current reaches a spi programmable maximum level. control is achieved by comparing the output of the cu rrent sense amplifier with a spi programmed dac value. the maxi comparator disables all gate drivers configured as ignition drivers when the dac maxi setting is exceeded. when a maxi event occurs, the m axi bit in the fault status register is set and the maxi pin is asserted (high). when using a 20 m resistor as the current sense resistor, the gain select of the differential amplifier connected to rsp and rsn, should be set to a gain of 2, via the spi command message spark command (command 0100, hex 4), control bit 6 =1. when using a 40 m resistor as the current sense resistor, the gain select of the differential amplifier connected to rsp and rsn, should be set to a gain of 1, via the spi command message spark command (command 0100, hex 4), control bit 6 =0. this is also the default value. the maxi fault bit in the spi fa ult status register is cleared when the maxi condition no longer exists and the spi fault status register has been read by the mcu. in v10 mode, the maxi pin is configured as an input to receive the maxi signal from a second mc33810 device in the system. in this mode a input maxi signal has effectively the same control as an inte rnal maxi signal. further information is provided in the v10 mode application section of this specification. table 11. nominal current dac select dac command bits<4,3,2,1,0> nomi current (a) differential voltage (mv rs = 20 m (gain = 2) differential voltage (mv rs = 40 m (gain = 1) 00000 3.00 60 120 00001 3.25 65 130 00010 3.50 70 140 00011 3.75 75 150 00100 4.00 80 160 00101 4.25 85 170 00110 4.50 90 180 00111 4.75 95 190 01000 5.00 100 200 01001 5.25 105 210 01010 5.50 110 220 01011 5.75 115 230 01100 6.00 120 240 01101 6.25 125 250 01110 6.50 130 260 01111 6.75 135 270 10000 7.00 140 280 10001 7.25 145 290 10010 7.50 150 300 10011 7.75 155 310 10100 8.00 160 320 10101 8.25 165 330 10110 8.50 170 340 10111 8.75 175 350 11000 9.00 180 360 11001 9.25 185 370 11010 9.50 190 380 11011 9.75 195 390 11100 10.00 200 400 11101 10.25 205 410 11110 10.50 210 420 11111 10.75 215 430 table 11. nominal current dac select dac command bits<4,3,2,1,0> nomi current (a) differential voltage (mv rs = 20 m (gain = 2) differential voltage (mv rs = 40 m (gain = 1) analog integrated circuit device data 22 freescale semiconductor 33810 functional device operation operational modes end of spark filter bits the ringing at the end of the spark signatures waveform can cause erroneous detection of the end of spark event. to eliminate the effect of this ri nging, a low pass filter with variable time values can be selected. four time values for the low pass filter have been provided with a zero value indicating that no low pass filtering is to be used. the end of spark filter bits specify a 0, 4s, 16s, or 32s time interval to sample the spark ignition coil primary current to ignore the ringing at the end of spark. general purpose gate driver mode each gate driver can be individually configured as a general purpose gate driver (gpgd) and controlled from the parallel ginx input pins, spi driver on/off command or may be programmed through the spi for a specific frequency and duty cycle output (pwm). in general purpose gate driver mode the gate drivers have the following features: ? gate driver for discrete external mosfet ? off state open load detect ? on state short circuit protection ? programmable drain threshold and duration timer for short fault detection ? pwm frequency/duty cycle controller in gpgd mode the gdx output is a current controlled output driver with slew rate control, gate to source clamp, passive pull-down resistor and a drain to gate clamp for switching inductive loads. driver on /off command the driver on/off command, bits 4 through 7 control gate drivers that have been mode select command programmed as gpgd. a logic 1 in bits 4 through 7 will command the specific output on . a logic 0 in the appropriate bit location commands the specific output off. also contained in the driver on/off command are spi control bits for the integrated lsd output drivers. further information on lsd control is provided in the low si de injector driver section of the data sheet. note: gate drivers programmed to ignition mode have parallel input control only, and cannot be turned off and on via spi commands. gpgd short threshold voltage command each gpgd driver is capable of detecting an open load in the off state and shorted load in the on state. all faults are reported through the spi communication. for open load detection, a current source is placed between the fbx pin and ground of the ic. an open load fault is reported when the fbx voltage is less than the 2.5 v threshold. open load fault detect threshold is set internally to 2.5 v and may not be programmed. a shorted load fault is reported when the fbx pin voltage is greater than t he programmed short threshold voltage. the short to battery fault thre shold voltage of the external mosfet is programmed via the gpgd short threshold voltage command. table 14 illustrates the bit pattern to select a particular threshold. drain voltages less than the selected threshold are considered normal operation. drain voltages greater than the sele cted threshold voltage are considered faulted. table 12. maximum current dac select dac command bit analog integrated circuit device data freescale semiconductor 23 33810 functional device operation operational modes gpgd short timer command the gpgd short timer command allows the user to select the duration of time that the drain voltage is allowed to be greater than the program ed threshold voltage without causing shutdown. external mosfets with drain voltages greater than the programed th reshold for longer than the fault duration timer are shutdown. timer durations are listed in table 15 . notes: tolerance on this fault timer setting is 10% after using the calibration command. gpgd fault operation command the gpgd fault operation co mmand sets the operating parameters for the gate drivers under faulted conditions. a short fault is said to be ?detected? when the drain source voltage, vds, of the exter nal mosfet, exceeds the spi programmed short threshold voltage. the short fault is said to be ?declared? when the v ds over-voltage lasts longer than the spi programmed ?fault timer.? (short duration time > fault timer programmed value) each gate driver is individually set to either, restore to the pre-fault state, or shutdown wh en a short fault is declared. by setting the retry/shutdown bit in the gpgd fault operation command to logic 1 the specific output will try to go back to the pre-fault state when the faul t is no longer declared, after a programmed ?inhibit time?. the retry strategy will cause the output to try to return to the pre-fault state on a 1% dut y cycle basis. for example: if the fault timer is set to 120 s and a fault is declared (drain voltage greater than the programmed threshold for greater than 120 s), the gdx output driver will be forced off for 12ms. after 12ms has elapsed, if the inputs, ginx or spi, have not tried to shut off the particular gdx output in the interim, the gdx output will try to set the external driver on again (the pre- fault state). a continued declared fault on the output would result in another 12ms shutdown period. by setting the retry/shutdown bit in the gpgd fault operation command to logic 0 the specific output will shutdown and remain off when the short fault is declared. only a reissue of the turn on command, via spi or ginx, will force the output to try and turn on again. in the event that a gpgd is selected as a pwm controller and a short occurs on the output, the output retry strategy forces the output to a 1% du ty cycle based on the fault timer setting. for example: if the fault timer is set to 120 s and a fault is detected (drain volt age greater than programmed threshold), the pwm output will be commanded off for 12ms and commanded on again at the next pwm cycle. care should be taken to select a fault timer that is shorter than the minimum duty cycle on time of the pwm controller. selecting a fault timer that is longer will allow the pwm controller to continue to drive the external mosfet into a shorted load. pwm frequency/duty cycle command the pwmx freq & duty cycle command is use to program the gdx outputs with a frequency and duty cycle. table 16 defines the user selectable output frequency. the frequency and duty cycle may be updated at any time using the pwm freq&dc command, however the update will only begin on the next pwm rising edge time. once the pwm freq & dc registers are programmed and the pwm controller is enabled through the mode command the pwm outputs are turned on and off via the ginx pin or the spi gpgd on/off command control bit. all parallel and serial on and off command updates to the pwm controller are synchronous with the rising edge of the previous pwm period. the truth table for gdx control in general purpose mode is provided in table 8 . the duty cycle of the pwm output s is controlled by bits 0- 6, inclusive. the duty cycle valu e is 1% per binary count from 1-100 with counts of 101-127 defaulting to 100%. for example, sending spi command 101001000001100 would set gd1, pwm output to 10hz and 12% duty cycle. table 14. fbx fault threshold select gpgd v ds flt bits fbx fault threshold select 000 0.5v 001 1.0v 010 1.5v 011 2.0 (default) 100 2.5v 101 3.0v 110 no change 111 no change table 15. fbx short fault timer gpgd flt timer bits fault timer select 000 30s 001 60s 010 120s 011 240s (default) 100 480s 101 960s 110 no change 111 no change analog integrated circuit device data 24 freescale semiconductor 33810 functional device operation operational modes . notes: tolerance on selected frequency is 10% after using the calibration command. shorts to battery and open load faults will not be detected for frequency and duty cycle combinations inconsistent with fault timers. table 17. pre-driver gdx output control v10 mode v10 mode provides a method for monitoring 10 ignition events while using only two current sense resistors. this is achieved using three mc33810 devices. two mc33810 devices are programmed as normal ignition mode outputs and one is programmed as a v10 ignition mode output. the ignition gate driver outputs are partitioned into two banks of five outputs each (see figure 10 ). each bank contains one or two driver(s) from the v10 device. drivers in the v10 device are grouped in two?s (gd0&gd2, gd1&gd3). current from each v10 mode igbt group is monitored by the appropriate normal mode device (see figure 10 ). the maxi signal from one normal mode device is ported to the v10 mode maxi in put pin. likewise the maxi signal from the second normal mode device is ported to the v10 mode nomi input pin. t he v10 mode nomi/maxi inputs are used as maxi shutdown signals for the appropriate ignition gate drive group. v10 mode contains the same features as ignition mode gate drivers with the following exceptions: ? nomi/maxi configured as input pins ? maxi shutdown for gpgd disabled ? nomi/maxi comparators disabled in v10 mode, spark command bits 7 and 8 (gain select, overlapping dwell) are disabled. these two features are achieved through the normal mode devices. rsn and rsp must be grounded in v10 mode. table 16. frequency select pwm freq&dc command bit analog integrated circuit device data freescale semiconductor 25 33810 functional device operation operational modes figure 10. v10 mode low side injector driver the four open drain low side injector drivers are designed to control various automotive loads such as injectors, solenoids, lamps, relays and unipolar stepper motors. each driver includes off and on state open load detection, short circuit protection and diagnostics. the injector drivers are individually controlled through the on/off spi input command table 20 or parallel input pins din0 to din3. serial and parallel control of the out put state is determined by the logical or of the spi serial bit and the dinx parallel input pins. all four outputs are disabled when the outen input pin is high regardless of the state of the spi control bit or the state of the dinx pin. all four injector drivers are not affected by the selection of the gate driver?s three modes of operation (ignition mode, general purpose mode, v10 mode). on /off control command to program the individual out put of the 33810 on or off, a 16-bit serial stream of data is entered into the si pin. the first 4 bits of the control word are used to identify the on / off command. bit 0 through bit 3 of the on/off control command turn on or off the specific output driver. injector driver fault commands fault protection strategies fo r the injector drivers are programmed by the spi lsd fault command. bit 8 through 11 determine the type of short circuit protection to be used, bits 0 through 7 set the open load strategy. short-circuit protection consis ts of three strategies. all strategies utilize current limiting as an active element to protect the output dr iver from failure.the t lim and timer options are used to enhance the short circuit protection strategy of the injector driv ers. the timer protection scheme uses a low duty cycle in the event of a short-circuit. the t lim gin 0 go 0 gin 1 go 1 gin 2 go 2 gin 3 go 3 logic 4 gin (0-3) nomi maxi rs1 igbt1 (0-3) ic 3 ?child? ic 2 ?parent? gin 0 go 0 gin 1 go 1 gin 2 go 2 gin 3 go 3 logic 4 gin nomi maxi rsp (0-3) gin 0 go 0 gin 1 go 1 gin 2 go 2 gin 3 go 3 logic 4 gin (0-3) rsp1 nomi maxi ic 1 ?parent? bank 2 bank 1 rsp2 igbt 2 (0-3) rs2 ign 1 ign 2 gate drive 0 gate drive 1 gate drive 2 gate drive 3 gate drive 0 gate drive 1 gate drive 2 gate drive 3 nomi maxi nomi maxi nomi maxi igbt1 4 igbt1 5 igbt2 6 igbt2 7 nomi comparator maxi comparator logic buffer logic buffer logic buffer logic buffer logic buffer logic buffer maxi comparator nomi comparator nomi disabled maxi disabled child comparator inputs tied to gnd nomi1 to up maxi1 to up maxi2 to up nomi2 to up vtni vtmi vtni vtmi vtmi vtni note: for ?child? input nomi is for channel 1&3, input maxi is for channel 0&2 analog integrated circuit device data 26 freescale semiconductor 33810 functional device operation operational modes protection circuit uses the junc tion temperature of the output driver to determine the fault. both methods may be used together or individually. timer protection the first protection scheme uses a low on to off duty cycle to protect the output dr iver. the low duty cycle allows the device to cool so that the maximum junction temperatures are not exceeded. during a shor t condition, the device enters current limit. the driver will shutdown for short conditions lasting longer than the current limit timer (~60 s) temperature limit (t lim ) the second scheme senses the temperature of the individual output driver. duri ng a short event the device enters current limit and will rema in in current limit until the output driver temperatur e limit is exceeded ( t lim ). at this point, the device will shutdown until the junction temperature falls below the hysteresis temperature value. the t lim hysteresis value is listed in th e previous specification tables. the third method combines both protection schemes into one. during a short event the device will enter current limit. the output driver will shutdown for short conditions lasting longer than the current limit time r. in the event that the output driver temperature is hig her than maximum specified temperature the out put will shutdown. the shutdown/retry bit allows the user to determine how the drivers will respond to each short circuit strategy. table 18 provides fault operation for all three strategies. outputs may be used in parallel to drive higher current loads provided the turn-off energy of the load does not exceed the energy rating of a single output driver (100mj maximum). table 18. injector driver (outx) fault operation output driver diagnostics. short to battery, temperature limit ( t lim ) and open load faults are reported through t he all status response message table 21 . off open load pull-down current enable bits an open load on the output driver is detected by the voltage level on the drain of the mosfet in the off state. internal to the device is a 75 a pull-down current sink. in the event of an open load the drain voltage is pulled low. when the voltage crosses the threshold, and open load is detected. the pull-down current source may be disabled by bit 0 through bit 3 in the lsd fault command. with the driver off and the off open load bit disabled, the off open load fault status bit will be logic 0. on open load enable bits the on state open load enable bit allows the user to determine an on state open lo ad. when the on state open load bit disabled, the on state fault bit is always logic 0. on open load is determined by monitoring the current through the outx mosfet. in the on stat e, currents less than 20 to 200ma are considered open. shutdn retry bit 11 tlim bit 10 fault timer bit 9 operation during short fault 1 0 x timer only, outputs will retry on period out0-out3 = 60 s on, ~10ms off 1 1 0 t lim only, outputs will retry on t lim hysteresis. 1 1 1 timer and t lim , outputs will retry on period and driver temperature below threshold. out0-out3= 60 s on, ~10ms off 0 0 x timer only, outputs will not retry on period out0-out3 = 60 s on, off 0 1 0 t lim only, outputs will not retry on tlim hysteresis. 0 1 1 timer and t lim , outputs will not retry on period or t lim . out0-out3 = 60 s on, off analog integrated circuit device data freescale semiconductor 27 33810 functional device operation operational modes table 19. injectordriver diagnostics clock calibration command in cases where an accurate time base is required, the user must calibrate the internal timers using the clock calibration command (refer to table 20 ) . after the 33810 device receives the calibration command, the device expects to receive a 32 s logic [0] calibration pulse on the cs pin. the pulse is used to calibrate the internal clock. any spi message may be sent during the 32 s calibration chip select. because the oscillator frequency may shift up to 35% with temperature, calibration is required for an accurate time base. the calibration command should be used to update the device on a periodic basis. spi command summary the spi commands are defined as 16 bits with 4 address control bits and 12 command data bits. there are 12 separate commands that are used to se t operational parameters of device. the operational parameters are stored internally in 16 bit registers. table 20 defines the commands and default state of the internal registers at por. spi commands may be sent to the device at any time in normal state. messages sent are acted upon on the rising edge of the cs input. . program state fault fault bits off state open load pull dwn on state open load en bit driver on/off output stb stg open outx batt short fault outx off open fault outx on open fault fault reported 0 x off stb 0 0 0 no fault 0 x off stg 0 0 0 no fault 0 x off open 0 0 0 no fault 1 x off stb 0 0 0 no fault 1 x off stg 0 1 0 open load 1 x off open 0 1 0 open load x 0 on stb 1 0 0 short to batt x 0 on stg 0 0 0 no fault x 0 on open 0 0 0 no fault x 1 on stb 1 0 0 short to batt x 1 on stg 0 0 1 open load x 1 on open 0 0 1 open load table 20. spi command message set and default state command control address bits command bits hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read registers command 0 0 0 0 0 1 0 1 0 <0000> internal register address 0 0 0 0 all status command 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 spi check command 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mode select command 1 0 0 0 1 <0000> ign/gp mode select set to ign mode <0> v10 en disab <0> ovr/ undr vtg x x <0> pwm3 en disab <0> pwm2 en disab <0> pwm1 en disab <0> pwm0 en disab analog integrated circuit device data 28 freescale semiconductor 33810 functional device operation operational modes lsd fault command 2 0 0 1 0 <10x> lsd flt operation shutdn,tlim,timer retry on timer and no tlim x <1> out3 on open load enabl <1> out2 on open load enabl <1> out1 on open load enabl <1> out0 on open load enabl <1> out3 off open load enabl <1> out2 off open load enabl <1> out1 off open load enabl <1> out0 off open load enabl driver on/off command 0 = off, 1 = on 3 0 0 1 1 x x x x <0000> gpgd off (ignored in ignition mode) <0000> outx driver off spark command 4 0 1 0 0 <100> max dwell timer maxdwell default=32 ms (in ignition mode only) <0> max dwell en disab <0> over lap dwell disab <0> gain sel gain = 1 <0> soft shut dn en disab <0> open 2 ed clmp disab <11> open secondary osflt =100 s <01> end spark threshold vpwr +5.5 v end spark filter 5 0 1 0 1 x x x x x x x x x x <01> end spark thresh 4.0 s dac command 6 0 1 1 0 <1000> maxi dac threshold maxi=14 a <100> overlap setting overlap 50% <01010> nomi dac threshold nomi=5.5 a gpgd short threshold voltage command 7 0 1 1 1 <011> short to batt v fb3 vth = 2.0 v <011> short to batt v fb2 vth = 2.0 v <011> short to batt v fb1 vth = 2.0 v <011> short to batt v fb0 vth = 2.0 v gpgd short duration timer command 8 1 0 0 0 <011> short to batt t fb3 timer = 240 s <011> short to batt t fb2 timer = 240 s <011> short to batt t fb1 timer = 240 s <011> short to batt t fb0 timer = 240 s gpgd fault operation select command 9 1 0 0 1 <1111> retry/shutdown bit retry on fault x x x x <0000> shutdown drivers on maxi disabled pwm0 to pwm3 freq & dc command a 1 0 1 0 <00> pwmx address pwm0 <000> pwm frequency 10 hz <0000000> pwm duty cycle 0% duty cycle invalid command b 1 0 1 1 x x x x x x x x x x x x invalid command c 1 0 1 1 x x x x x x x x x x x x invalid command d 1 1 0 1 x x x x x x x x x x x x clock calibration command e 1 1 1 0 x x x x x x x x x x x x invalid command f 1 1 1 1 x x x x x x x x x x x x table 20. spi command message set and default state command control address bits command bits hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 analog integrated circuit device data freescale semiconductor 29 33810 functional device operation operational modes spi response registers fault reporting is accomplished through the spi interface. all logic [1]s received by the mcu via the so pin indicate faults. all logic [0]s received by the mcu via pin indicate no faults. timing between two write words must be greater than the fault timer to allow adequate time to sense and report the proper fault status. . table 21. spi response messages 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next so response to: spi check command 0 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 next so response to hex1 to hex a commands and read all status command all status response reset cor sor nmf ign3 fault ign2 fault ign1 fault ign0 fault gp3 fault gp2 fault gp1 fault gp0 fault out3 fault out2 fault out1 fault out0 fault next so response to read register command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address <0000> all status register 0 = no fault, 1 = fault reset cor sor nmf ign3 fault ign2 fault ign1 fault ign0 fault gp3 fault gp2 fault gp1 fault gp0 fault out3 fault out2 fault out1 fault out0 fault address <0001> out1, out0 fault register 0 = no fault, 1 = fault reset cor over voltage low voltage 0 0 0 0 out1 tlim fault out1 batter y short fault out1 off open fault out1 on open fault out0 tlim fault out0 batter y short fault out0 off open fault out0 on open fault address <0010> out3, out2 fault register 0 = no fault, 1 = fault reset cor over voltage low voltage 0 0 0 0 out3 tlim fault out3 batter y short fault out3 off open fault out3 on open fault out2 tlim fault out2 batter y short fault out2 off open fault out2 on open fault address <0011> gpgd mode fault register 0 = no fault, 1 = fault reset cor over voltage low voltage 0 0 0 0 gp3 short circuit fault gp3 open load fault gp2 short circuit fault gp2 open load fault gp1 short circuit fault gp1 open load fault gp0 short circuit fault gp0 open load fault address <0100> ign mode fault register 0 = no fault, 1 = fault reset cor over voltage low voltage ign3 maxi fault ign3 max dwell fault ign3 open secon d fault ign2 maxi fault ign2 max dwell fault ign2 open secon d fault ign1 maxi fault ign1 max dwell fault ign1 open secon d fault ign0 maxi fault ign0 max dwell fault ign0 open secon d fault address <0101> mode command register reset cor over voltage low voltage ign/gp mode select v10 en ovr vtg x x pwm 3 en pwm 2 en pwm 1 en pwm 0 en address <0110> lsd fault command register reset cor over voltage low voltage lsd flt operation shutdn,tlim,timer x out3 on open load out2 on open load out1 on open load out0 on open load out3 off open load out2 off open load out1 off open load out0 off open load address <0111> drvr on/off command reg reset cor over voltage low voltage x x x x gpgd (20) outx driver (20) address <1000> spark command register reset cor over voltage low voltage max dwell timer maxdwell max dwell en over lap dwell gain sel soft shut dn en open 2 ed clmp open secondary end spark threshold notes 20. these bits refer to command on or off state in the command re gisters, not the state of the respective output lines. these bi ts are not to be confused with the ignition mode state whic h is controlled only by the parallel inputs and their state is not reflected in these bits. analog integrated circuit device data 30 freescale semiconductor 33810 functional device operation operational modes address <0101> end spark filter register reset cor over voltage under voltage x x x x x x x x x x end spark filter address <1010> dac command register reset cor over voltage low voltage maxi dac threshold overlap setting nomi dac threshold address <1011> gpgd fbx short to battery threshold voltage register reset cor over voltage low voltage short to batt v fb3 short to batt v fb2 short to batt v fb1 short to batt v fb0 address <1100> gpgd fbx short to battery threshold timer register reset cor over voltage low voltage short to batt t fb3 short to batt t fb2 short to batt t fb1 short to batt t fb0 address <1101> gpgd fault operation register reset cor over voltage low voltage retry/shutdown bit x x x x shutdown drivers on imax address <1110> pwm freq&dc register (last channel programmed) reset cor over voltage low voltage pwmx address pwm frequency pwm duty cycle address <1111> revision id, trim, clock cal. reset cor ovr vtg low voltage 3 rev 2 id 1 0 x x cal too hi cal too low x x trim parity error trim lock out legend cor = command out of range sor = supply out of range nmf = set when faults occur on v10 mode maxi and nomi inputs and v10 mode ignition driver are off. table 21. spi response messages analog integrated circuit device data freescale semiconductor 31 33810 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ek (pb-free) suffix 32-pin 98asa10556d issue d analog integrated circuit device data 32 freescale semiconductor 33810 packaging package dimensions . ek (pb-free) suffix 32-pin 98asa10556d issue d analog integrated circuit device data freescale semiconductor 33 33810 packaging package dimensions ek (pb-free) suffix 32-pin 98asa10556d issue d analog integrated circuit device data 34 freescale semiconductor 33810 revision history revision history revision date description of changes 3.0 10/2007 ? initial release 4.0 2/2008 ? fixed several typos throughout document ? changed static electrical characteri stics, table 3, digital interface, out_en leakage current to v dd, maximum from 10 to 50 a. ? reworded table 15. ? added table 16 back (it was inadvertently deleted. ? added ?ignition &? to tile in table 4. 5.0 8/2008 ? updated package drawing. 6.0 12/2008 ? parameter changes to gate drive source current, spark duration comparator threshold, nomi trip threshold accuracy, maxi trip point during overlapping dwell, comparator hysteresis voltage, short to battery fault detection voltage threshold, output off open load detection current, and input logic-voltage hysteresis. ? made change to end of spark filter time select ? changed orderable part number from pc z33810ek/r2 to mcz33810ek/r2 on page 1. ? revised exposed pad pin definition in table 1, page 3. ? changed package outline drawing to 98asa10556d. mc33810 rev. 6.0 12/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006 - 2008. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com |
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